1. Field of the Invention
The present invention relates to a sense amplifier arrangement for semiconductor memories, including random access memories (RAMs), and read only memories (ROMs), among others, which utilize intersecting rows and columns for access to individual memory cells.
2. Description of the Prior Art
Generally, in a dynamic RAM utilizing a one transistor per cell system, the voltage changes occurring in the data lines are minute and, therefore, a "sense amplifier circuit" (output detector) is necessary for the evaluation and regeneration of data, where the sense amplifier circuit is capable of detecting the read-out data with satisfactory sensitivity and amplifying this data reliably.
In a typical sense amplifier arrangement, a distable sensing amplifier is employed for sensing the voltage difference between the potential on the two conductors of the bit line. Each column conductor may also be referred to as half of the bit line. In the case of a dynamic RAM, this difference results from a sharing of the charge read from a reference cell onto one half of the bit line and from an accessed storage cell on the other half of the bit line. To refresh the electrical signals read out of the memory cells, switchable circuitry is included which is responsive to a timing signal generated after the sense amplifier has latched into a stable state.
One particular prior art dynamic RAM arrangement, disclosed in U.S. Pat. No. 4,069,475 issued to C. E. Boettcher on Jan. 17, 1978, eliminates the need for separate restore timing signals by deriving such signals from a bistable sensing amplifier when the bistable sensing amplifier has switched sufficiently to exceed the turn-on threshold of the corresponding restore bypass switch. Such an arrangement also permits a reduction in the power dissipation of the sense amplifier.
An alternative arrangement is disclosed in U.S. Pat. No. 4,286,178 issued to G. R. Mohan Rao et al on Aug. 25, 1981. Like the above-described Boettcher arrangement, the Rao et al sense amplifier circuit employs a bistble sense amplifier circuit at the center of each column. However, instead of a single pair of cross-coupled driver transistors forming the bistable circuit, dual parallel pairs are used in the Rao et al arrangement. One pair used in the initial sensing has a long channel length so that the pair may be more readily matched, while the other pair, used later in the cycle for driving the zero-going side of the column line to ground, has a shorter channel to enhance speed.
As memory devices require higher packing density, higher speed, and lower power dissipation, the sense amplifiers become more critical. Some prior circuits exhibit high power dissipation and overly long charging and discharging times for the digit lines, while others require high instantaneous current and critical clock timing. Further, as the number of bits increases, the cell size decreases, the magnitude of the storage capacitor in each cell, of necessity, decreases, and the capacitance of the digit lines increase due to the increase in the number of cells on a digit line. These factors reduce the magnitude of the data signal which exists on a digit line, and the speed with which it can be sensed. Similar considerations apply to ROMs, EPROMs, and other memory devices.
Thus, it would be desirable to provide an improved sense amplifier arrangement for memory configurations utilizing row and column conductors for memory cell access with improved signal transfer speed, without unduly increasing the power dissipation.